Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
A study of scalar compilation techniques for pipelined supercomputers
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Retargetable instruction scheduling for pipelined processors
Retargetable instruction scheduling for pipelined processors
Probabilistic register allocation
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs
CC '92 Proceedings of the 4th International Conference on Compiler Construction
Register allocation over the program dependence graph
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
GURRR: a global unified resource requirements representation
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Register allocation sensitive region scheduling
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
CRAIG: a practical framework for combining instruction scheduling and register assignment
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Spill-free parallel scheduling of basic blocks
Proceedings of the 28th annual international symposium on Microarchitecture
Proceedings of the 28th annual international symposium on Microarchitecture
Experiences with Cooperating Register Allocation and Instruction Scheduling
International Journal of Parallel Programming
A Register Allocation Technique Using Register Existence Graph
ICPP '97 Proceedings of the international Conference on Parallel Processing
A Spill Code Placement Framework for Code Scheduling
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Integrated Instruction Scheduling and Register Allocation Techniques
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Understanding and Improving Register Assignment
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Register Saturation in Superscalar and VLIW Codes
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Register saturation in instruction level parallelism
International Journal of Parallel Programming
Tetris: a new register pressure control technique for VLIW processors
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Fast, frequency-based, integrated register allocation and instruction scheduling
Software—Practice & Experience
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
On the Optimality of Register Saturation
Electronic Notes in Theoretical Computer Science (ENTCS)
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Parallelism improvements of software pipelining by combining spilling with rematerialization
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
Optimal and heuristic global code motion for minimal spilling
CC'13 Proceedings of the 22nd international conference on Compiler Construction
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