The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Register allocation via graph coloring
Register allocation via graph coloring
A schedular-sensitive global register allocator
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Register allocation over the program dependence graph
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
GURRR: a global unified resource requirements representation
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Proceedings of the 28th annual international symposium on Microarchitecture
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Unification of register allocation and instruction scheduling in compilers for fine-grain parallel architectures
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Cooperative instruction scheduling with linear scan register allocation
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Integrated instruction scheduling and fine-grain register allocation for embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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An algorithm for integrating instruction scheduling and register allocation must support mechanisms for detecting excessive register and functional unit demands and applying reductions for lessening these demands. The excessive demands for functional units can be detected by identifying the instructions that can execute in parallel, and can be reduced by scheduling some of these instructions sequentially. The excessive demands for registers can be detected on-the-fly while scheduling by maintaining register pressure values or may be detected prior to scheduling using an appropriate representation such as parallel interference graphs or register reuse dags. Reductions in excessive register demands can be achieved by live range spilling or live range splitting. However, existing integrated algorithms that are based upon mechanisms other than register reuse dags do not employ live range splitting. In this paper, we demonstrate that for integrated algorithms, register reuse dags are more effective than either on-the-fly computation of register pressure or interference graphs and that live range splitting is more effective than live range spilling. Moreover the choice of mechanisms greatly impacts on the performance of an integrated algorithm.