Integrated instruction scheduling and fine-grain register allocation for embedded processors

Authors:
Dae-Hwan Kim;Hyuk-Jae Lee
Affiliations:
School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea;School of Electrical Engineering and Computer Science, Seoul National University, Seoul, Korea
Venue:
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2006

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Abstract

This paper proposes a new integration technique, called IRIS (Integrated Register allocation and Instruction Scheduling), to combine instruction scheduling and register allocation. Both register allocation and instruction scheduling are performed simultaneously at each variable reference where the selection between serialization by scheduling and spilling by register allocation is determined. To make a right selection, the costs of serialization and spilling are estimated with a cost model proposed to reduce the complexity of the estimation. Experiments show that IRIS achieves significant improvements when compared to widely-used existing techniques.