Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Region Scheduling: An Approach for Detecting and Redistributing Parallelism
IEEE Transactions on Software Engineering
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Global instruction scheduling for superscalar machines
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Fortran compiler for the FPS-164 scientific computer
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A schedular-sensitive global register allocator
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
Integrating program transformations in the memory-based synthesis of image and video algorithms
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register file port requirements of transport triggered architectures
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
GURRR: a global unified resource requirements representation
IR '95 Papers from the 1995 ACM SIGPLAN workshop on Intermediate representations
Code optimization techniques for embedded DSP microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CRAIG: a practical framework for combining instruction scheduling and register assignment
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Allocating registers in multiple instruction-issuing processors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Spill-free parallel scheduling of basic blocks
Proceedings of the 28th annual international symposium on Microarchitecture
Proceedings of the 28th annual international symposium on Microarchitecture
Register allocation for predicated code
Proceedings of the 28th annual international symposium on Microarchitecture
Partitioned register file for TTAs
Proceedings of the 28th annual international symposium on Microarchitecture
A register allocation technique using guarded PDG
ICS '96 Proceedings of the 10th international conference on Supercomputing
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Experiences with Cooperating Register Allocation and Instruction Scheduling
International Journal of Parallel Programming
Register allocation in structured programs
Proceedings of the sixth annual ACM-SIAM symposium on Discrete algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register-sensitive selection, duplication, and sequencing of instructions
ICS '01 Proceedings of the 15th international conference on Supercomputing
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Computation in the Context of Transport Triggered Architectures
International Journal of Parallel Programming
IEEE Transactions on Computers
A Register Allocation Technique Using Register Existence Graph
ICPP '97 Proceedings of the international Conference on Parallel Processing
Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Copy Elimination for Parallelizing Compilers
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
A Spill Code Placement Framework for Code Scheduling
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Integrated Instruction Scheduling and Register Allocation Techniques
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Understanding and Improving Register Assignment
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Register Saturation in Superscalar and VLIW Codes
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Signal Processing - From signal processing theory to implementation
Efficient instruction scheduling for a pipelined architecture
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Register saturation in instruction level parallelism
International Journal of Parallel Programming
A framework for reducing instruction scheduling overhead in dynamic compilers
CASCON '06 Proceedings of the 2006 conference of the Center for Advanced Studies on Collaborative research
Tetris: a new register pressure control technique for VLIW processors
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Fast, frequency-based, integrated register allocation and instruction scheduling
Software—Practice & Experience
Periodic register saturation in innermost loops
Parallel Computing
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
On the Optimality of Register Saturation
Electronic Notes in Theoretical Computer Science (ENTCS)
Detecting bugs in register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Extended linear scan: an alternate foundation for global register allocation
CC'07 Proceedings of the 16th international conference on Compiler construction
Combined code motion and register allocation using the value state dependence graph
CC'03 Proceedings of the 12th international conference on Compiler construction
Eliminating false phase interactions to reduce optimization phase order search space
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Register allocation with instruction scheduling for VLIW-architectures
Programming and Computing Software
The Journal of Supercomputing
Catching and identifying bugs in register allocation
SAS'06 Proceedings of the 13th international conference on Static Analysis
Cooperative instruction scheduling with linear scan register allocation
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
Integrated instruction scheduling and fine-grain register allocation for embedded processors
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Optimal and heuristic global code motion for minimal spilling
CC'13 Proceedings of the 22nd international conference on Compiler Construction
Scheduling independent liveness analysis for register binding in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting phase inter-dependencies for faster iterative compiler optimization phase order searches
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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We present a new framework in which considerations of both register allocation and instruction scheduling can be applied uniformly and simultaneously. In this framework an optimal coloring of a graph, called the parallel interference graph, provides an optimal register allocation and preserves the property that no false dependences are introduced, thus all the options for parallelism are kept for the scheduler to handle. For this framework we provide heuristics for trading off parallel scheduling with register spilling.