Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
A schedular-sensitive global register allocator
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
The multiflow trace scheduling compiler
The Journal of Supercomputing - Special issue on instruction-level parallelism
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Proceedings of the 28th annual international symposium on Microarchitecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
tcc: a system for fast, flexible, and high-level dynamic code generation
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Quality and speed in linear-scan register allocation
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Advanced compiler design and implementation
Advanced compiler design and implementation
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
A high performance Erlang system
Proceedings of the 2nd ACM SIGPLAN international conference on Principles and practice of declarative programming
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
Linear Scan Register Allocation in the Context of SSA Form and Register Constraints
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Combining Register Allocation and Instruction Scheduling
Combining Register Allocation and Instruction Scheduling
Unification of register allocation and instruction scheduling in compilers for fine-grain parallel architectures
Effective instruction scheduling with limited registers
Effective instruction scheduling with limited registers
Optimized interval splitting in a linear scan register allocator
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
Cooperative instruction scheduling with linear scan register allocation
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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Instruction scheduling and register allocation are two of the most important optimization phases in modern compilers as they have a significant impact on the quality of the generated code. Unfortunately, the objectives of these two optimizations are in conflict with one another. The instruction scheduler attempts to exploit instruction-level parallelism and requires many operands to be available in registers. On the other hand, the register allocator wants register pressure to be kept low so that the amount of spill code can be minimized. Currently these two phases are done separately, typically in three passes: prepass scheduling, register allocation and postpass scheduling. But this separation can lead to poor results. Previous works attempted to solve the phase-ordering problem by combining the instruction scheduler with graph-coloring-based register allocators. The latter tend to be computationally expensive. Linear-scan register allocators, on the other hand, are simple, fast and efficient. In this paper, we describe our effort to integrate instruction scheduling with a linear-scan allocator. Furthermore, our integrated optimizer is able to take advantage of execution frequencies obtained through profiling. Our integrated register allocator and instruction scheduler achieved good code quality with significantly reduced compilation times. On the SPEC2000 benchmarks running on a 900 MHz ItaniumII, compared with OpenIMPACT, we halved the time spent in instruction scheduling and register allocation with negligible impact on execution times. Copyright © 2007 John Wiley & Sons, Ltd.