Code scheduling and register allocation in large basic blocks
ICS '88 Proceedings of the 2nd international conference on Supercomputing
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Proceedings of the 28th annual international symposium on Microarchitecture
Reorganizing global schedules for register allocation
ICS '99 Proceedings of the 13th international conference on Supercomputing
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Integrated Instruction Scheduling and Register Allocation Techniques
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Linear Scan Register Allocation in a High-Performance Erlang Compiler
PADL '02 Proceedings of the 4th International Symposium on Practical Aspects of Declarative Languages
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Region-based register allocation for epic architectures
Region-based register allocation for epic architectures
Effective instruction scheduling with limited registers
Effective instruction scheduling with limited registers
Fast, frequency-based, integrated register allocation and instruction scheduling
Software—Practice & Experience
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Linear scan register allocation is an attractive register allocation algorithm because of its simplicity and fast running time. However, it is generally felt that linear scan register allocation yields poorer code than allocation schemes based on graph coloring. In this paper, we propose a pre-pass instruction scheduling algorithm that improves on the code quality of linear scan allocators. Our implementation in the Trimaran compiler-simulator infrastructure shows that our scheduler can reduce the number of active live ranges that the linear scan allocator has to deal with. As a result, fewer spills are needed and the quality of the generated code is improved. Furthermore, compared to the default scheduling and graph-coloring allocator schemes found in the IMPACT and Elcor components of Trimaran, our implementation with our pre-pass scheduler and linear scan register allocator significantly reduced compilation times.