Evaluating the use of profiling by a region-based register allocator
Proceedings of the 2002 ACM symposium on Applied computing
Increasing the number of effective registers in a low-power processor using a windowed register file
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
IEEE Transactions on Computers
Profile-based global live-range splitting
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Tetris: a new register pressure control technique for VLIW processors
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
WCET analysis of instruction caches with prefetching
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Exploiting virtual registers to reduce pressure on real registers
ACM Transactions on Architecture and Code Optimization (TACO)
Languages and Compilers for Parallel Computing
Analyzing the worst-case execution time for instruction caches with prefetching
ACM Transactions on Embedded Computing Systems (TECS)
Techniques for Region-Based Register Allocation
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
ACM Transactions on Architecture and Code Optimization (TACO)
Virtual registers: reducing register pressure without enlarging the register file
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Cooperative instruction scheduling with linear scan register allocation
HiPC'05 Proceedings of the 12th international conference on High Performance Computing
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