Prefetching in supercomputer instruction caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Contrasting characteristics and cache performance of technical and multi-user commercial workloads
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
A worst case timing analysis technique for instruction prefetch buffers
Selected papers of the short notes session on Euromicro '94
Wrong-path instruction prefetching
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Prefetching using Markov predictors
Proceedings of the 24th annual international symposium on Computer architecture
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
ACM Computing Surveys (CSUR)
Retargetable static timing analysis for embedded software
Proceedings of the 14th international symposium on Systems synthesis
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Region-based register allocation for epic architectures
Region-based register allocation for epic architectures
WCET Centric Data Allocation to Scratchpad Memory
RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
A new WCET estimation algorithm based on instruction cache and prefetching combined model
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Reconciling real-time guarantees and energy efficiency through unlocked-cache prefetching
Proceedings of the 50th Annual Design Automation Conference
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Instruction prefetching is an effective technique to reduce the instruction cache miss latency for improving the average-case performance. For real-time systems, however, the use of instruction prefetching will only besuitable if a reasonably tight worst-case performance of programs using instruction prefetching can be predicted. This paper presents an approach to modeling and computing the worst-case instruction cache performance with prefetching. Our experimental results indicate that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance, thus leading to increased time variation for real-time computing. Also, we find that the prefetching distance can significantly impact the worst-case performance analysis with instruction prefetching. Particularly, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized (i.e., optimal).