A new WCET estimation algorithm based on instruction cache and prefetching combined model

Authors:
Guowei Wu;Lin Yao
Affiliations:
Software College of Dalian University of Technology, Dalian, China;Software College of Dalian University of Technology, Dalian, China
Venue:
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
Year:
2004

Citing 2
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WCET analysis of instruction caches with prefetching

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A Graph-Theory Algorithm for WCET Estimation

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Analyzing the worst-case execution time for instruction caches with prefetching

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Abstract

It is necessary to compute the execution time upper bound of embedded hard real-time program under the worst condition in embedded system design, which decides how hardware and software to partition and how to schedule process. Modern microprocessor which uses instruction cache memory and instruction pre-fetching increases the difficulty to compute the upper bound accurately. A new estimation method of embedded software performance based on instruction cache and pre-fetching model is proposed, which uses control flow graph and cache conflict graph and combine instruction pre-fetching into instruction cache analysis. It makes the execution time upper bound estimation under worst condition more accurate.