Prefetching in supercomputer instruction caches
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
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ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
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Selected papers of the short notes session on Euromicro '94
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MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
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HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
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RTSS '05 Proceedings of the 26th IEEE International Real-Time Systems Symposium
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RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
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ECRTS '06 Proceedings of the 18th Euromicro Conference on Real-Time Systems
A new WCET estimation algorithm based on instruction cache and prefetching combined model
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
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Time predictability is one of the most important design considerations for real-time systems. In this article, we study the impact of instruction prefetching on the worst-case performance of instruction caches. We extend the static cache simulation technique to model and compute the worst-case instruction cache performance with prefetching. The evaluation results show that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance. As a result, the time variation of computing is increased by instruction prefetching. Also, our experimental results indicate that the prefetching distance can significantly impact the worst-case performance of instruction caches with instruction prefetching. Specifically, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized.