Branch History Guided Instruction Prefetching

Authors:
Viji Srinivasan;Edward S. Davidson;Gary S. Tyson;Mark J. Charney;Thomas R. Puzak
Affiliations:
-;-;-;-;-
Venue:
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Year:
2001

Citing 0
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Abstract

Abstract: As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack ...