Integrating register allocation and instruction scheduling for RISCs

The Marion system for retargetable instruction scheduling

PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation

Global instruction scheduling for superscalar machines

PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation

The effect on RISC performance of register set size and structure versus code generation strategy

ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture

Efficient DAG construction and heuristic calculation for instruction scheduling

MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture

Software support for speculative loads

ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

Efficient superscalar performance through boosting

ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

Techniques for integrating parallelizing transformations and compiler-based scheduling methods

Proceedings of the 1992 ACM/IEEE conference on Supercomputing

Register allocation with instruction scheduling

PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation

Lifetime-sensitive modulo scheduling

PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation

A novel framework of register allocation for software pipelining

POPL '93 Proceedings of the 20th ACM SIGPLAN-SIGACT symposium on Principles of programming languages

A schedular-sensitive global register allocator

Proceedings of the 1993 ACM/IEEE conference on Supercomputing

Integrating program transformations in the memory-based synthesis of image and video algorithms

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Register allocation sensitive region scheduling

PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques

CRAIG: a practical framework for combining instruction scheduling and register assignment

PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques

Spill-free parallel scheduling of basic blocks

Proceedings of the 28th annual international symposium on Microarchitecture

An experimental study of several cooperative register allocation and instruction scheduling strategies

Proceedings of the 28th annual international symposium on Microarchitecture

A register allocation technique using guarded PDG

ICS '96 Proceedings of the 10th international conference on Supercomputing

Instruction scheduling for the Motorola 88110

MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture

Code generation for core processors

DAC '97 Proceedings of the 34th annual Design Automation Conference

Experiences with Cooperating Register Allocation and Instruction Scheduling

International Journal of Parallel Programming

Reorganizing global schedules for register allocation

ICS '99 Proceedings of the 13th international conference on Supercomputing

Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Register-sensitive selection, duplication, and sequencing of instructions

ICS '01 Proceedings of the 15th international conference on Supercomputing

A Dynamic Programming Approach to Optimal Integrated Code Generation

OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems

Global array reference allocation

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Handling Global Constraints in Compiler Strategy

International Journal of Parallel Programming

Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme

IEEE Transactions on Computers

Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures

IEEE Transactions on Computers

A Method for Register Allocation to Loops in Multiple Register File Architectures

IPPS '96 Proceedings of the 10th International Parallel Processing Symposium

Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs

IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium

Copy Elimination for Parallelizing Compilers

LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing

A Spill Code Placement Framework for Code Scheduling

LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing

Integrated Instruction Scheduling and Register Allocation Techniques

LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing

Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors

LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing

Array Reference Allocation Using SSA-Form and Live Range Growth

LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems

Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers

PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques

URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures

PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism

Integrated prepass scheduling for a Java Just-In-Time compiler on the IA-64 architecture

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization

Compiler optimization-space exploration

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization

Register allocation for optimal loop scheduling

CASCON '93 Proceedings of the 1993 conference of the Centre for Advanced Studies on Collaborative research: distributed computing - Volume 2

Efficient instruction scheduling for a pipelined architecture

ACM SIGPLAN Notices - Best of PLDI 1979-1999

A framework for reducing instruction scheduling overhead in dynamic compilers

CASCON '06 Proceedings of the 2006 conference of the Center for Advanced Studies on Collaborative research

Fast, frequency-based, integrated register allocation and instruction scheduling

Software—Practice & Experience

Detecting bugs in register allocation

ACM Transactions on Programming Languages and Systems (TOPLAS)

Extended linear scan: an alternate foundation for global register allocation

CC'07 Proceedings of the 16th international conference on Compiler construction

Register pressure aware scheduling for high level synthesis

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Catching and identifying bugs in register allocation

SAS'06 Proceedings of the 13th international conference on Static Analysis

Cooperative instruction scheduling with linear scan register allocation

HiPC'05 Proceedings of the 12th international conference on High Performance Computing

SARA: combining stack allocation and register allocation

CC'06 Proceedings of the 15th international conference on Compiler Construction

Gras: A general framework for combining automatic code generation and register allocation

Computer Languages

Scheduling expression DAGs for minimal register need

Computer Languages