Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Effectiveness of a machine-level, global optimizer
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Linear-time, optimal code scheduling for delayed-load architectures
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Efficient DAG construction and heuristic calculation for instruction scheduling
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Performance evaluation of instruction scheduling on the IBM RISC System/6000
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Lifetime-sensitive modulo scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Balanced scheduling: instruction scheduling when memory latency is uncertain
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
VLIW compilation techniques in a superscalar environment
PLDI '94 Proceedings of the ACM SIGPLAN 1994 conference on Programming language design and implementation
PA-RISC 2.0 architecture
Advanced compiler design and implementation
Advanced compiler design and implementation
Optimal instruction scheduling using integer programming
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Retargetable high-level alias analysis
POPL '86 Proceedings of the 13th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Code generation and reorganization in the presence of pipeline constraints
POPL '82 Proceedings of the 9th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Coding guidelines for pipelined processors
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
A Fine-Grain Parallelizing Compiler
A Fine-Grain Parallelizing Compiler
Local code generation and compaction in optimizing microcode compilers
Local code generation and compaction in optimizing microcode compilers
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
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As part of an effort to develop an optimizing compiler for a pipelined architecture, a code reorganization algorithm has been developed that significantly reduces the number of runtime pipeline interlocks. In a pass after code generation, the algorithm uses a dag representation to heuristically schedule the instructions in each basic block.Previous algorithms for reducing pipeline interlocks have had worst-case runtimes of at least O(n4). By using a dag representation which prevents scheduling deadlocks and a selection method that requires no lookahead, the resulting algorithm reorganizes instructions almost as effectively in practice, while having an O(n2) worst-case runtime.