Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Efficient instruction scheduling for a pipelined architecture
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Theory of linear and integer programming
Theory of linear and integer programming
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
A simple interprocedural register allocation algorithm and its effectiveness for LISP
ACM Transactions on Programming Languages and Systems (TOPLAS)
Algorithmic aspects of balancing techniques for pipelined data flow code generation
Journal of Parallel and Distributed Computing
Available instruction-level parallelism for superscalar and superpipelined machines
ASPLOS III Proceedings of the third international conference on Architectural support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
Compiling for dataflow software pipelining
Selected papers of the second workshop on Languages and compilers for parallel computing
Improving register allocation for subscripted variables
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
A timed Petri-net model for fine-grain loop scheduling
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Register allocation for software pipelined loops
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Register allocation via graph coloring
Register allocation via graph coloring
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Using a lookahead window in a compaction-based parallelizing compiler
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A compilation technique for software pipelining of loops with conditional jumps
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Scheduling Parallel Computations
Journal of the ACM (JACM)
Postpass Code Optimization of Pipeline Constraints
ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel processing: a smart compiler and a dumb machine
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A Fortran compiler for the FPS-164 scientific computer
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
A Code Mapping Scheme for Dataflow Software Pipelining
A Code Mapping Scheme for Dataflow Software Pipelining
Conversion of control dependence to data dependence
POPL '83 Proceedings of the 10th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Register Allocation, Renaming and Their Impact on Fine-Grain Parallelism
Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs
CC '92 Proceedings of the 4th International Conference on Compiler Construction
MICRO 14 Proceedings of the 14th annual workshop on Microprogramming
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Compaction-Based Parallelization
Compaction-Based Parallelization
Register allocation for optimal loop scheduling
Register allocation for optimal loop scheduling
On minimizing register usage of linearly scheduled algorithms with uniform dependencies
Computer Languages, Systems and Structures
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One of the major challenges in designing optimizing compilers, especially for scientific computation, is to take advantage of the parallelism in loops in order to obtain maximum speedup on parallel computer architectures. Optimal loop scheduling is therefore one of the most important topics studied by many computer scientists. However, how to allocate a minimum number of registers to support optimal loop scheduling for parallel architectures is less understood. In this report, we propose a simultaneous scheduling and register allocation approach for a parallelizing compiler. We have proved that the general problem of finding such an optimal scheduling together with register allocation is NP-complete. Then we propose a practical approach to divide the register allocation problem into two steps. The first step solves a minimum buffer allocation problem, which will find a time-optimal periodic schedule using a minimum number of buffers. We give a polynomial time algorithm to solve this problem. The second step analyzes the live ranges of the variables and uses coloring algorithms to reduce the register requirement by sharing. The algorithm has been implemented and used to test selected loops in benchmark programs. Testing results are reported.