Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
A data-flow driven resource allocation in a retargetable microcode compiler
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Spill code minimization techniques for optimizing compliers
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Coloring heuristics for register allocation
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
On the Minimization of Loads/Stores in Local Register Allocation
IEEE Transactions on Software Engineering
Integrating register allocation and instruction scheduling for RISCs
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Probabilistic register allocation
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Register allocation via graph coloring
Register allocation via graph coloring
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimal register assignment to loops for embedded code generation
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Journal of the ACM (JACM)
New methods to color the vertices of a graph
Communications of the ACM
A comment on index register allocation
Communications of the ACM
Register Allocation, Renaming and Their Impact on Fine-Grain Parallelism
Proceedings of the Fourth International Workshop on Languages and Compilers for Parallel Computing
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs
CC '92 Proceedings of the 4th International Conference on Compiler Construction
Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific)
Partitioning of Variables for Multiple-Register-File VLIW Architectures
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Cluster assignment of global values for clustered VLIW processors
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Load scheduling: reducing pressure on distributed register files for free
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Mobile Information Systems - Mobile and Wireless Networks
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Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocation for these architectures then becomes exceedingly important as spill code increases memory bandwidth demands and decreases performance, especially within loops. Previously, we have addressed the issue of finding an optimal allocation of variables to registers within loops for a consolidated register file model. In this paper, we extend that work to architectures where the available registers have been partitioned into multiple banks. Experimental results demonstrate that, while the optimal algorithm may be computationally prohibitive, heuristic versions obtain acceptable performances.