Register allocation in the SPUR Lisp compiler
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Global register allocation at link time
SIGPLAN '86 Proceedings of the 1986 SIGPLAN symposium on Compiler construction
Trapezoid graphs and their coloring
Discrete Applied Mathematics
New methods to color the vertices of a graph
Communications of the ACM
Register allocation by priority-based coloring
SIGPLAN '84 Proceedings of the 1984 SIGPLAN symposium on Compiler construction
An overview of the PL.8 compiler
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57)
Instruction scheduling beyond basic blocks
IBM Journal of Research and Development
Graph coloring register allocation for processors with multi-register operands
PLDI '90 Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
ACM Letters on Programming Languages and Systems (LOPLAS)
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Load/store range analysis for global register allocation
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reducing memory traffic with CRegs
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Abstract interpretation and low-level code optimization
PEPM '95 Proceedings of the 1995 ACM SIGPLAN symposium on Partial evaluation and semantics-based program manipulation
Code reuse in an optimizing compiler
Proceedings of the 11th ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications
A register allocation technique using guarded PDG
ICS '96 Proceedings of the 10th international conference on Supercomputing
Heuristics for register-constrained software pipelining
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Spill code minimization via interference region spilling
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Call-cost directed register allocation
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Fast, effective code generation in a just-in-time Java compiler
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Look-ahead allocation in the presence of branches
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Profile assisted register allocation
SAC '00 Proceedings of the 2000 ACM symposium on Applied computing - Volume 2
Improved spill code generation for software pipelined loops
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Fusion-based register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimization of available C compilers for the MC68HC11
ACM-SE 30 Proceedings of the 30th annual Southeast regional conference
IEEE Transactions on Computers
A Method for Register Allocation to Loops in Multiple Register File Architectures
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A Spill Code Placement Framework for Code Scheduling
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Register Saturation in Superscalar and VLIW Codes
CC '01 Proceedings of the 10th International Conference on Compiler Construction
A faster optimal register allocator
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Meta optimization: improving compiler heuristics with machine learning
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Register Constrained Modulo Scheduling
IEEE Transactions on Parallel and Distributed Systems
Coloring heuristics for register allocation
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Finding effective compilation sequences
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A fast, memory-efficient register allocation framework for embedded systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
A Progressive Register Allocator for Irregular Architectures
Proceedings of the international symposium on Code generation and optimization
A spill code minimization technique: application in the metrowerks starcore C compiler
International Journal of Parallel Programming
Register saturation in instruction level parallelism
International Journal of Parallel Programming
Tailoring Graph-coloring Register Allocation For Runtime Compilation
Proceedings of the International Symposium on Code Generation and Optimization
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Profile-based global live-range splitting
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Exploiting idle register classes for fast spill destination
Proceedings of the 22nd annual international conference on Supercomputing
Instruction Scheduling Across Control Flow
Scientific Programming
EMSOFT '08 Proceedings of the 8th ACM international conference on Embedded software
Register Bank Assignment for Spatially Partitioned Processors
Languages and Compilers for Parallel Computing
Register allocation deconstructed
Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems
Detecting bugs in register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Genetic programming applied to compiler heuristic optimization
EuroGP'03 Proceedings of the 6th European conference on Genetic programming
MIRS: modulo scheduling with integrated register spilling
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
Coloring-based coalescing for graph coloring register allocation
Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
Register allocation with instruction scheduling for VLIW-architectures
Programming and Computing Software
Register loading via linear programming
WADS'11 Proceedings of the 12th international conference on Algorithms and data structures
LCPC'05 Proceedings of the 18th international conference on Languages and Compilers for Parallel Computing
Catching and identifying bugs in register allocation
SAS'06 Proceedings of the 13th international conference on Static Analysis
Combining offline and online optimizations: register allocation and method inlining
APLAS'06 Proceedings of the 4th Asian conference on Programming Languages and Systems
Hybrid optimizations: which optimization algorithm to use?
CC'06 Proceedings of the 15th international conference on Compiler Construction
Scheduling expression DAGs for minimal register need
Computer Languages
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Global register allocation and spilling is commonly performed by solving a graph coloring problem. In this paper we present a new coherent set of heuristic methods for reducing the amount of spill code generated. This results in more efficient (and shorter) compiled code. Our approach has been compared to both standard and priority-based coloring algorithms, universally outperforming them.In our approach, we extend the capability of the existing algorithms in several ways. First, we use multiple heuristic functions to increase the likelihood that less spill code will be inserted. We have found three complementary heuristic functions which together appear to span a large proportion of good spill decisions. Second, we use a specially tuned greedy heuristic for determining the order of deleting (and hence coloring) the unconstrained vertices. Third, we have developed a “cleaning” technique which avoids some of the insertion of spill code in non-busy regions.