Spill code minimization techniques for optimizing compliers
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Register allocation via graph coloring
Register allocation via graph coloring
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
ACM Transactions on Programming Languages and Systems (TOPLAS)
Spill code minimization via interference region spilling
Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation
Quality and speed in linear-scan register allocation
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
Building an optimizing compiler
Building an optimizing compiler
Precise register allocation for irregular architectures
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimal spilling for CISC machines with few registers
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
ARM Architecture Reference Manual
ARM Architecture Reference Manual
Live Range Splitting in a Graph Coloring Register Allocator
CC '98 Proceedings of the 7th International Conference on Compiler Construction
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Optimistic register coalescing
ACM Transactions on Programming Languages and Systems (TOPLAS)
Optimized interval splitting in a linear scan register allocator
Proceedings of the 1st ACM/USENIX international conference on Virtual execution environments
MiBench: A free, commercially representative embedded benchmark suite
WWC '01 Proceedings of the Workload Characterization, 2001. WWC-4. 2001 IEEE International Workshop
A global progressive register allocator
Proceedings of the 2006 ACM SIGPLAN conference on Programming language design and implementation
Optimal register allocation for SSA-form programs in polynomial time
Information Processing Letters
Register allocation via coloring of chordal graphs
CATS '07 Proceedings of the thirteenth Australasian symposium on Theory of computing - Volume 65
Copy coalescing by graph recoloring
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
A fast cutting-plane algorithm for optimal coalescing
CC'07 Proceedings of the 16th international conference on Compiler construction
Extended linear scan: an alternate foundation for global register allocation
CC'07 Proceedings of the 16th international conference on Compiler construction
Register loading via linear programming
WADS'11 Proceedings of the 12th international conference on Algorithms and data structures
Studying optimal spilling in the light of SSA
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
| Hi-index | 0.00 |
Register allocation is a fundamental part of any optimizing compiler. Effectively managing the limited register resources of the constrained architectures commonly found in embedded systems is essential in order to maximize code quality. In this paper we deconstruct the register allocation problem into distinct components: coalescing, spilling, move insertion, and assignment. Using an optimal register allocation framework, we empirically evaluate the importance of each of the components, the impact of component integration, and the effectiveness of existing heuristics. We evaluate code quality both in terms of code performance and code size and consider four distinct instruction set architectures: ARM, Thumb, x86, and x86-64. The results of our investigation reveal general principles for register allocation design.