Understanding and Improving Register Assignment

  • Authors:
  • Cindy Norris;James B. Fenwick, Jr.

  • Affiliations:
  • -;-

  • Venue:
  • Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
  • Year:
  • 1999

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Abstract

Register allocation can decrease instruction-level parallelism by prohibiting the scheduler from reordering instructions. The impact of register assignment strategies on a subsequent scheduling phase is explored. A new register assignment strategy and experimental results are presented.