List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures

  • Authors:

  • Thomas Zeitlhofer;Bernhard Wess

  • Affiliations:

  • Institute of Communications and Radio-Frequency Engineering, Vienna University of Technology, Gusshausstrasse 25/389, A-1040 Vienna, Austria;Institute of Communications and Radio-Frequency Engineering, Vienna University of Technology, Gusshausstrasse 25/389, A-1040 Vienna, Austria

  • Venue:
  • Signal Processing - From signal processing theory to implementation
  • Year:
  • 2003

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Abstract

This article focuses on register assignment problems for heterogeneous register-set VLIW-DSP architectures. It is assumed that an instruction schedule has already been generated. The register assignment problem is equivalent to the well-known coloring of an interference graph. Typically, machine-related constraints are mapped onto the structure of the interference graph. Thereby favorable characteristics with regard to coloring, the interval graph properties, get lost. In contrast, we present an approach that does not change the structure of the interference graph. Constraints implied by heterogeneous architectures are mapped to a specific coloring problem that is known as list-coloring. Exploiting the interval graph properties of the interference graph, we derive a list-coloring algorithm that allows us to generate optimum solutions even for large basic blocks. The proposed technique can also be applied to similar resource assignment problems like functional unit assignment.