Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
On the scheduling of variable latency functional units
Proceedings of the eleventh annual ACM symposium on Parallel algorithms and architectures
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Register allocation via coloring
Computer Languages
Optimal register sharing for high-level synthesis of SSA form programs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Classical techniques for register allocation and binding require the definition of the program execution order, since a partial ordering relation between operations must be induced to perform liveness analysis through data-flow equations. In High Level Synthesis (HLS) flows this is commonly obtained through the scheduling task. However for some HLS approaches, such a relation can be difficult to be computed, or not statically computable at all, and adopting conventional register binding techniques, even when feasible, cannot guarantee maximum performances. To overcome these issues we introduce a novel scheduling-independent liveness analysis methodology, suitable for dynamic scheduling architectures. Such liveness analysis is exploited in register binding using standard graph coloring techniques, and unlike other approaches it avoids the insertion of structural dependencies, introduced to prevent run-time resource conflicts in dynamic scheduling environments. The absence of additional dependencies avoids performance degradation and makes parallelism exploitation independent from the register binding task, while on average not impacting on area, as shown through the experimental results.