Implementing Precise Interrupts in Pipelined Processors
IEEE Transactions on Computers
Computer architecture (2nd ed.): a quantitative approach
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A Variable Latency Pipelined Floating-Point Adder
Euro-Par '96 Proceedings of the Second International Euro-Par Conference on Parallel Processing-Volume II
Design of a Computer—The Control Data 6600
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Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the Conference on Design, Automation and Test in Europe
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