A data-flow driven resource allocation in a retargetable microcode compiler
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Register allocation via graph coloring
Register allocation via graph coloring
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
ACM Transactions on Programming Languages and Systems (TOPLAS)
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Code generation for fixed-point DSPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Precise register allocation for irregular architectures
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Register allocation for irregular architectures
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Optimistic Register Coalescing
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
DSP processor/compiler co-design: a quantitative approach
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A generalized algorithm for graph-coloring register allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
A retargetable register allocation framework for embedded processors
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A Progressive Register Allocator for Irregular Architectures
Proceedings of the international symposium on Code generation and optimization
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
Transactions on High-Performance Embedded Architectures and Compilers II
Approximations for Aligned Coloring and Spillage Minimization in Interval and Chordal Graphs
APPROX '09 / RANDOM '09 Proceedings of the 12th International Workshop and 13th International Workshop on Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques
CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
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In this paper, Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we developed a modified algorithm for optimal coalescing that helps a register allocator for an embedded processor to better handle such heterogeneity of the register architecture. In the experiment, an existing register allocator was able to achieve up to 10% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.