Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Generalization of the Sethi-Ullman algorithm for register allocation
Software—Practice & Experience
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Digital signal processing applications with the TMS320 family (vol. 2)
Digital signal processing applications with the TMS320 family (vol. 2)
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Using register-transfer paths in code generation for heterogeneous memory-register architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Generation of Optimal Code for Arithmetic Expressions
Journal of the ACM (JACM)
The Generation of Optimal Code for Stack Machines
Journal of the ACM (JACM)
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
Code Generation for a One-Register Machine
Journal of the ACM (JACM)
Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
Efficient Computation of Expressions with Common Subexpressions
Journal of the ACM (JACM)
Journal of the ACM (JACM)
Instruction Sets for Evaluating Arithmetic Expressions
Journal of the ACM (JACM)
Code-generation for machines with multiregister operations
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Code Generation for Embedded Processors
Code Generation for Embedded Processors
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Rapid development of optimized DSP code from a high level description through software estimations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast memory bank assignment for fixed-point digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Register coalescing techniques for heterogeneous register architecture with copy sifting
ACM Transactions on Embedded Computing Systems (TECS)
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
Transactions on High-Performance Embedded Architectures and Compilers II
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This paper examines the problem of code-generation for Digital Signal Processors (DSPs). We make two major contributions. First, for an important class of DSP architectures, we propose an optimal O(n) algorithm for the tasks of register allocation and instruction scheduling for expression trees. Optimality is guaranteed by sufficient conditions derived from a structural representation of the processor Instruction Set Architecture (ISA). Second, we develop heuristics for the case when basic blocks are Directed Acyclic Graphs (DAGs).