A data-flow driven resource allocation in a retargetable microcode compiler
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Improvements to graph coloring register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
ACM Transactions on Programming Languages and Systems (TOPLAS)
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Code generation for fixed-point DSPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constraint driven code selection for fixed-point DSPs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Instruction Sets for Evaluating Arithmetic Expressions
Journal of the ACM (JACM)
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Optimistic Register Coalescing
PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A generalized algorithm for graph-coloring register allocation
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Reducing instruction bit-width for low-power VLIW architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Many embedded processors have complex, irregular architectures resulting from the customization for the maximum performance and energy efficiency of target applications. One such example is the heterogeneous register architecture, which has fast, small-sized register files, for their specific uses, distributed over the data paths between different functional units. Although this architectural design may be good at achieving the H/W design goal of high speed, small area and low power, it requires highly expensive algorithms for optimal code generation. This is primarily because multiple registers contained in each file come with many different constraints subject to their design purposes, and often their names are aliased with each other; thus the final code quality is very sensitive to how properly such aliased, heterogeneous registers are utilized in every instruction. In this work, we propose a code generation approach to attack this complex problem. The experiments reveal that our approach is fast, practically running in polynomial time. In comparison with the related work, it achieves approximately 13% of code size reduction and 16% of speed increase.