Instruction scheduling using genetic algorithms
Instruction scheduling using genetic algorithms
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Evolutionary algorithms in theory and practice: evolution strategies, evolutionary programming, genetic algorithms
Using register-transfer paths in code generation for heterogeneous memory-register architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
Constraint driven code selection for fixed-point DSPs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Register allocation for common subexpressions in DSP data paths
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Compiler Design
Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
Low-Energy DSP Code Generation Using a Genetic Algorithm
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Operation scheduling for parallel functional units using genetic algorithms
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Optimal vs. heuristic integrated code generation for clustered VLIW architectures
SCOPES '08 Proceedings of the 11th international workshop on Software & compilers for embedded systems
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
Transactions on High-Performance Embedded Architectures and Compilers II
Integrated Code Generation for Loops
ACM Transactions on Embedded Computing Systems (TECS)
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The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting special hardware features. Due to the irregular architectures present in today's DSPs there is a need of compilers which are capable of performing a phase coupling of the highly interdependent code generation subtasks and a graph based code selection. In this paper we present a code generator which performs a graph based code selection and a complete phase coupling of code selection, instruction scheduling (including compaction) and register allocation. In addition, our code generator takes into account effects of the subsequent address code generation phase. In order to solve the phase coupling problem and to handle the problem complexity, our code generator is based on a genetic algorithm. Experimental results for several benchmarks and an MP3 application for two DSPs show the effectiveness and the retargetability of our approach. Using the presented techniques, the number of execution cycles is reduced by 51% on average for the M3-DSP and by 38% on average for the ADSP2100 compared to standardtechniques1.