Instruction selection using binate covering for code size optimization

  • Authors:

  • Stan Liao;Srinivas Devadas;Kurt Keutzer;Steve Tjiang

  • Affiliations:

  • Department of EECS, Massachusetts Institute of Technology;Department of EECS, Massachusetts Institute of Technology;Advanced Technology Group, Synopsys, Inc.;Advanced Technology Group, Synopsys, Inc.

  • Venue:
  • ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1995

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Abstract

We address the problem of instruction selection in code generation for embedded DSP microprocessors. Such processors have highly irregular data-paths, and conventional code generation methods typically result in inefficient code. Instruction selection can be formulated as directed acyclic graph (DAG) covering. Conventional methods for instruction selection use heuristics that break up the DAG into a forest of trees and then cover them independently. This breakup can result in suboptimal solutions for the original DAG. Alternatively, the DAG covering problem can be formulated as a binate covering problem, and solved exactly or heuristically using branch-and-bound methods. We show that optimal instruction selection on a DAG in the case of accumulator-based architectures requires a partial scheduling of nodes in the DAG, and we augment the binate covering formulation to minimize spills and reloads. We show how the irregular data transfer costs of typical DSP data-paths can be modeled in the binate covering formulation.