Exploring Hypermedia Processor Design Space

  • Authors:

  • Chunho Lee;Johnson Kin;Miodrag Potkonjak;William H. Mangione-Smith

  • Affiliations:

  • Department of Computer Science, University of California, Los Angeles, CA, USA;Department of Electrical Engineering, University of California, Los Angeles, CA, USA;Department of Computer Science, University of California, Los Angeles, CA, USA;Department of Electrical Engineering, University of California, Los Angeles, CA, USA

  • Venue:
  • Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
  • Year:
  • 2001

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Abstract

Distributed hypermedia systems that support collaboration are important emerging tools for creation, discovery, management and delivery of information. These systems are becoming increasingly desired and practical as other areas of information technologies advance. A framework is developed for efficiently exploring the hypermedia design space while intelligently capitalizing on tradeoffs between performance and area. We focus on a category of processors that are programmable yet optimized to a hypermedia application.The key components of the framework presented in this paper are a retargetable instruction-level parallelism compiler, instruction level simulators, a set of complete media applications written in a high level language, and a media processor synthesis algorithm. The framework addresses the need for efficient use of silicon by exploiting the instruction-level parallelism found in media applications by compilers that target multiple-instruction-issue processors.Using the developed framework we conduct an extensive exploration of the design space for a hypermedia application. We find that there is enough instruction-level parallelism in the typical media and communication applications to achieve highly concurrent execution when throughput requirements are high. On the other hand, when throughput requirements are low, there is little value in multiple-instruction-issue processors. Increased area does not improve performance enough to justify the use of multiple-instruction-issue processors when throughput requirements are low.The framework introduced in this paper is valuable in making early architecture design decisions such as cache and issue width trade-off when area is constrained, and the number of branch units and instruction issue width.