Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Media architecture: general purpose vs. multiple application-specific programmable processor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Storage assignment optimizations to generate compact and efficient code on embedded DSPs
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Function inlining under code size constraints for embedded processors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Memory bank customization and assignment in behavioral synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimized address assignment for DSPs with SIMD memory accesses
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Exploring Hypermedia Processor Design Space
Journal of VLSI Signal Processing Systems - Special issue on multimedia signal processing
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Compiler Support for Scalable and Efficient Memory Systems
IEEE Transactions on Computers
Design of a high-throughput low-power IS95 Viterbi decoder
Proceedings of the 39th annual Design Automation Conference
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Instruction selection using binate covering for code size optimization
Readings in hardware/software co-design
Readings in hardware/software co-design
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
A Framework for Parallelizing Load/Stores on Embedded Processors
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
ACM SIGARCH Computer Architecture News
Proceedings of the 40th annual Design Automation Conference
Memory Organization for Improved Data Cache Performance in Embedded Processors
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Instruction Scheduling for Low Power
Journal of VLSI Signal Processing Systems
Comparing a genetic algorithm penalty function and repair heuristic in the DSP application domain
AIA'06 Proceedings of the 24th IASTED international conference on Artificial intelligence and applications
Minimizing bank selection instructions for partitioned memory architecture
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Minimal placement of bank selection instructions for partitioned memory architectures
ACM Transactions on Embedded Computing Systems (TECS)
Memory Offset Assignment for DSPs
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Function Inlining in Embedded Systems with Code Size Limitation
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Design of a 20-Mb/s 256-state viterbi decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing code size via page selection optimization on partitioned memory architectures
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
| Hi-index | 0.00 |
An architectural feature commonly found in digital signal processors (DSPs) is multiple data-memory banks. This feature increases memory bandwidth by permitting multiple memory accesses to occur in parallel when the referenced variables belong to different memory banks and the registers involved are allocated according to a strict set of conditions. Unfortunately, current compiler technology is unable to take advantage of the potential increase in parallelism offered by such architectures. Consequently, most application software for DSP systems is hand-written -- a very time-consuming task.We present an algorithm which attempts to maximize the benefit of this architectural feature. While previous approaches have decoupled the phases of register allocation and memory bank assignment, our algorithm performs these two phases simultaneously. Experimental results demonstrate that our algorithm substantially improves the code quality of many compiler-generated and even hand-written programs.