A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
IMPACT: an architectural framework for multiple-instruction-issue processors
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Custom-fit processors: letting applications define architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Heterogeneous built-in resiliency of application specific programmable processors
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
MicroUnity's MediaProcessor Architecture
IEEE Micro
Hardware-Software Interactions on Mpact
IEEE Micro
Treegion Scheduling for Highly Parallel Processors
Euro-Par '97 Proceedings of the Third International Euro-Par Conference on Parallel Processing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A technique to determine power-efficient, high-performance superscalar processors
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Instruction Set Design and Optimizations for Address Computation in DSP Architectures
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Function unit specialization through code analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Localized watermarking: methodology and application to operation scheduling
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.01 |
In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to synthesize a high performance machine for an application. Using the framework we evaluate the validity of the fundamental assumption behind the development of application-specific programmable processors. Application-specific processors are based on the idea that applications differ from each other in key architectural parameters, such as the available instruction-level parallelism, demand on various hardware components (e.g. cache memory units, register files) and the need for different number of functional units. We found that the framework introduced in this paper can be valuable in making early design decisions such as area and architectural trade-off, cache and instruction issue width trade-off under area constraint, and the number of branch units and issue width.