Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Shall We Repair? Genetic AlgorithmsCombinatorial Optimizationand Feasibility Constraints
Proceedings of the 5th International Conference on Genetic Algorithms
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
AE '95 Selected Papers from the European conference on Artificial Evolution
Computers & Mathematics with Applications
Hi-index | 0.00 |
To increase memory bandwidth, many programmable Digital Signal Processors (DSPs) employ two on-chip data memories. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to occur in parallel. Exploiting dual memory banks, however, is a challenging problem for compilers. This, in part, is due to the instruction-level parallelism, small numbers of registers, and highly specialized register capabilities of most DSPs. In this paper, we present a new methodology based on a genetic algorithm (GA) for assigning data to dual-bank memories. Our approach is global, and integrates several important issues in memory assignment within a single model. Special effort is made to identify those data objects that could potentially benefit from an assignment to a specific memory, or perhaps duplication in both memories. As part of our experimentation, we compare the effectiveness of a repair heuristic which consist in transforming infeasible solutions into feasible ones, with a penalty functions that seeks to degrade the fitness of infeasible individuals based on their degree of constraint violation. Our results show that the repair operator out-performs the penalty function. Tests on DSPstone benchmarks show that the GA is able to achieve a 54% reduction in the number of memory cycles and a reduction in the range of 7% to 42% in the total number of cycles.