Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Tree automata for code selection
Acta Informatica
New ideas for solving covering problems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Instruction selection using binate covering for code size optimization
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
Compiler Design
A Retargetable C Compiler: Design and Implementation
A Retargetable C Compiler: Design and Implementation
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Phase coupling and constant generation in an optimizing microcode compiler
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
Logic synthesis for vlsi design
Logic synthesis for vlsi design
Proceedings of the 39th annual Design Automation Conference
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
Proceedings of the conference on Design, automation and test in Europe
Processor Description Languages
Processor Description Languages
Design Methodology for Offloading Software Executions to FPGA
Journal of Signal Processing Systems
Tuning a protocol processor architecture towards DSP operations
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
| Hi-index | 0.01 |
Embedded processors in electronic systems typically are tuned to a few applications. Development of processor-specific compilers is prohibitively expensive and, as a result, such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a processor model that captures the connectivity, the parallelism, and all architectural peculiarities of an embedded processor. We also implemented a retargetable and optimizing compiler working on this model. We present the graph-based processor model, and formally define the code generation task as binding the intermediate representation of an application to this model. We also present a new method for code selection, based on this processor model, that is capable of handling directed acyclic graphs instead of trees.