Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Register assignment through resource classification for ASIP microcode generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Design of heterogeneous ICs for mobile and personal communication systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A transformation-based approach for storage optimization
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
High-level synthesis and codesign methods: an application to a videophone codec
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
WWW based structuring of codesigns
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
ISDL: an instruction set description language for retargetability
DAC '97 Proceedings of the 34th annual Design Automation Conference
Transformational partitioning for co-design of multiprocessor systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware/software partitioning for multi-function systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Subsetting Behavioral Intellectual Property for Low Power ASIP Design
Journal of VLSI Signal Processing Systems - Special issue on system level design
Application-specific memory management for embedded systems using software-controlled caches
Proceedings of the 37th Annual Design Automation Conference
Reconfigurable Filter Coprocessor Architecture for DSP Applications
Journal of VLSI Signal Processing Systems
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A model for system-level timed analysis and profiling
Proceedings of the conference on Design, automation and test in Europe
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Efficient code generation for in-house DSP-cores
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Industrial approach in design methodologies for mobile communications systems
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Instruction-Set Matching and GA-based Selection for Embedded-Processor Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Flexible modeling environment for embedded systems design
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Partitioning of embedded applications onto heterogeneous multiprocessor architectures
Proceedings of the 2003 ACM symposium on Applied computing
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Register coalescing techniques for heterogeneous register architecture with copy sifting
ACM Transactions on Embedded Computing Systems (TECS)
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
Transactions on High-Performance Embedded Architectures and Compilers II
Register files constraint satisfaction during scheduling of DSP code
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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