Generating instruction sets and microarchitectures from applications
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Scheduling techniques to enable power management
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Exploiting regularity for low-power design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Memory modeling for system synthesis
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Behavioral Synthesis for low Power
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
Journal of VLSI Signal Processing Systems
Proceedings of the 13th international symposium on Low power electronics and design
A scalable synthesis methodology for application-specific processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Journal of Supercomputing
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Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor from a more general processor, such as a DSP. Although not as effective as an ASIC solution, instruction subsetting provides much of the power savings while maintaining some level of programmability. Beyond energy savings, instruction subsetting also offers the opportunity to reduce the design cycle through the re-use of existing processor intellectual property including behavioral and structural designs, hardware simulators, application code, and compilers. We synthesized 9 ASIPs through place and route and found that a poorly chosen instruction set may consume more than 4 times the energy of an ASIP with a proper instruction set choice. This finding will allow designers to consider another set of trade-offs in their hardware/software design space exploration.