Constraint analysis for DSP code generation

Authors:
Bart Mesman;Adwin H. Timmer;Jef L. van Meerbergen;Jochen A. G. Jess
Affiliations:
Eindhoven Univ. of Technology, Eindhoven, The Netherlands;Philips Research Laboratory, Eindhoven, The Netherlands;Eindhoven Univ. of Technology, Eindhoven, The Netherlands;Eindhoven Univ. of Technology, Eindhoven, The Netherlands
Venue:
Readings in hardware/software co-design
Year:
2001

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Abstract

Code generation methods for digital signal-processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of resource and timing constraints. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low register requirements.