Minimizing register requirements under resource-constrained rate-optimal software pipelining

  • Authors:

  • R. Govindarajan;Erik R. Altman;Guang R. Gao

  • Affiliations:

  • Dept. of Computer Science, Memorial Univ. of Newfoundland, St. John's, A1C 5S7, CANADA;Dept. of Electrical Engineering, McGill University, Montreal, H3A 2A7, CANADA;School of Computer Science, McGill University, Montreal, H3A 2A7, CANADA

  • Venue:
  • MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
  • Year:
  • 1994

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Abstract

In this paper we address the following software pipelining problem: given a loop and a machine architecture with a fixed number of processor resources (e.g. function units), how can one construct a software-pipelined schedule which runs on the given architecture at the maximum possible iteration rate (a` la rate-optimal) while minimizing the number of registers?The main contributions of this paper are:•First, we demonstrate that such problem can be described by a simple mathematical formulation with precise optimization objectives under periodic linear scheduling framework. The mathematical formulation provides a clear picture which permits one to visualize the overall solution space (for rate-optimal schedules) under different sets of constraints.•Secondly, we show that a precise mathematical formulation and its solution does make a significant performance difference! We evaluated the performance of our method against three other leading contemporary heuristic methods: Huff's Slack Scheduling, Wang, Eisenbeis, Jourdan and Su's FRLC, and Gasperoni and Schwiegelshohn's modified list scheduling. Experimental results show that the method described in this paper performed significantly better than these methods.