SAMP: a general purpose processor based on a self-timed VLIW structure
ACM SIGARCH Computer Architecture News
Retargetable assembly code generation by bootstrapping
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Implementations of IF-statements in the TODOS microarchitecture synthesis system
Proceedings of the IFIP WG10.2/WG10.5 Workshops on Synthesis for Control Dominated Circuits
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Open-ended system for high-level synthesis of flexible signal processors
EURO-DAC '90 Proceedings of the conference on European design automation
Using compilers for heterogeneous system design
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Constraint analysis for DSP code generation
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Proceedings of the 12th international symposium on System synthesis
Register files constraint satisfaction during scheduling of DSP code
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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