A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic generation of self-test programs—a new feature of the MIMOLA design system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
PASCAL user manual and report
A performance evaluation of the Intel 80286
ACM SIGARCH Computer Architecture News
A user-microprogrammable, local host computer with low-level parallelism
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
Computer
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Microcode Generation for Flexible Parallel Target Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Processor Description Languages
Processor Description Languages
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A high-performance, general purpose processor has been designed, using various technology independent methods to improve performance. Its structure offers a large degree of parallelism and is adjusted to the application. A novel control unit, which asynchronously controls instruction execution by tokens, allows the evaluation of very complex expressions without any reference to clock cycles. The main memory communicates via 4 ports with the processor and avoids a bottleneck in accessing data. The processor performance is measured and compared with several commercial systems.