Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Microcode Generation for Flexible Parallel Target Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Formal Techniques for Hardware Allocation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
EURO-DAC '91 Proceedings of the conference on European design automation
Affine transformations for multi-dimensional signal processing on ASIC regular arrays
EURO-DAC '91 Proceedings of the conference on European design automation
Automated generation of DSP program development tools using a machine description formalism
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
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CATHEDRAL-2nd is a new synthesis environment, intended to be the follow-up of our current CATHEDRAL-II approach. It is tuned towards the mapping of complex medium sample rate DSP applications onto flexible microcoded architectures. An important novel feature, is the increase in architectural freedom. As opposed to the formerly predefined limited set of execution units (EXUs) in CATHEDRAL-II, the system supports more flexibility in the composition of EXUs. The paper treats the impact of this feature on scheduling, hardware assignment and memory management.