Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Introduction to algorithms
High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Exact coloring of real-life graphs is easy
DAC '97 Proceedings of the 34th annual Design Automation Conference
A constraint driven approach to loop pipelining and register binding
Proceedings of the conference on Design, automation and test in Europe
Microcode Generation for Flexible Parallel Target Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Register files constraint satisfaction during scheduling of DSP code
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Constraint analysis for DSP code generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Phase coupled operation assignment for VLIW processors with distributed register files
Proceedings of the 14th international symposium on Systems synthesis
Static resource models of instruction sets
Proceedings of the 14th international symposium on Systems synthesis
Scheduling coarse-grain operations for VLIW processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Load scheduling: reducing pressure on distributed register files for free
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity of the available register files. Traditional methods that schedule spill code to satisfy storage capacity have difficulty satisfying the timing constraints. The method presented in this paper analyses the combination of limited register file capacity, resource- and timing constraints during scheduling. Value lifetimes are serialized until all capacity constraints are guaranteed to be satisfied after scheduling. Experiments in the FACTS environment show that we efficiently obtain high quality instruction schedules for inner-most loops of DSP algorithms.