Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Exact coloring of real-life graphs is easy
DAC '97 Proceedings of the 34th annual Design Automation Conference
Microcode Generation for Flexible Parallel Target Architectures
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Constraint analysis for DSP code generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Constraint analysis for code generation: basic techniques and applications in FACTS
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Proceedings of the 12th international symposium on System synthesis
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Algorithms in digital signal processing (DSP) impose tight timing constraints that the compiler has to respect while considering the limited capacity of the available register files in a target DSP processor. Traditional code generation methods that schedule spill code to satisfy storage capacity may take many iterations and are usually not capable of satisfying the timing constraints. In this paper we present a new method to handle register file capacity constraints during scheduling. The method identifies potential bottlenecks for register binding and subsequently serializes the lifetimes of values until it can be guaranteed that all capacity constraints will be satisfied after scheduling. Experiments show that we efficiently obtain high quality instruction schedules for DSP kernels.