DSP design tool requirements for embedded systems: a telecommunications industrial perspective
Journal of VLSI Signal Processing Systems - Special issue on design environments for DSP
CodeSyn: a retargetable code synthesis system (abstract)
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
A new approach to pipeline optimisation
EURO-DAC '90 Proceedings of the conference on European design automation
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor
Proceedings of the conference on Design, automation and test in Europe - Volume 2
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The core tasks of retargetable code generation are instruction-set matching and selection for a given application program and a DSP/ASIP processor. In this paper, we utilize a model of target architecture specification that employs both behavioral and structural information, to facilitate this process. The matching method is based on a pattern tree structure of instructions. This tree structure , generated automatically, is implemented by using a pattern queue and a flag table. The matching process is efficient since it bypasses many patterns in the tree which do not match at certain nodes in the DFG of given application program. Two genetic algorithms are implemented for pattern selection: a pure GA which uses standard GA operators, and a GA with backtracking which employs variable- length chromosomes. Optimal or near-optimal pattern selection is obtained in a reasonable period of time for a wide range of application programs.