DSP processor/compiler co-design: a quantitative approach

Authors:
V. Zivojnovic;S. Pees;C. Schlager;M. Willems;R. Schoenen;H. Meyr
Affiliations:
Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany;Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany;Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany;Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany;Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany;Aachen University of Technology,Integrated Systems for Signal Processing, Templergraben 55, IS2 611810, 52056 Aachen, Germany
Venue:
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Year:
1996

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Abstract

In the paper the problem of processor/compiler codesign for digital signal processing and embedded systems is discussed. The main principle we follow is the top-down approach characterized by extensive simulation and quantitative performance evaluation of processor and compiler. Although well established in the design of state-of-the-art general purpose processors and compilers, this approach is rarely followed by leading producers of signal and embedded processors. As a consequence, the matching between the processor and the compiler is low. In the paper we focus on three main components of our exploration environment-benchmarking methodology (DSPstone), fast processor simulation (SuperSim), and machine description (LISA). Most of the paper is devoted to the technique of compiled processor simulation. The speedup obtained allows an exploration of a much larger design space than it was possible with standard processor simulators.