UltraSPARC: Compiling for Maximum Floating Point Performance
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
DSP processor/compiler co-design: a quantitative approach
ISSS '96 Proceedings of the 9th international symposium on System synthesis
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Modern reduced-instruction-set computer chips have features that lay the groundwork for great performance. They boast circuits that can work at clock frequencies ranging to 300 MHz, pipelines built to continually execute independent operations, and the ability to execute multiple instructions in a single clock cycle. The potential of this hardware can only be realized by sophisticated compiler technology. The best approach to optimal computing performance is to design a processor architecture and a compiler concurrently