Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test Pattern Generation for API Faults in RAM
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Testing SRAM-Based Content Addressable Memories
IEEE Transactions on Computers
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
With the increase in memory density, neighborhood pattern sensitive faults (NPSFs) are not only an important fault model for DRAMs but will also become so for SRAMs. NPSFs can be considered generalized versions of simple-cell faults and two-cell coupling faults, whereby the extra cells involved in the NPSF are required to have an enabling value. A new coupling fault model, the disturb fault (CFdst) has been published (van de Goor, 1996). It has the property that it is more consistent with the true behavior of the memory, while tests for CFdsts can be designed such that they also cover idempotent CFs. It is the purpose of this paper to extend the concept of CFdsts to NPSFs based on CFdsts ( i.e, the Disturb NPSFs ) and present tests for those DNPSFs. It will be shown that the tests for DNPSFs are more efficient than those of the traditional tests for NPSFs while they also cover the faults of the traditional NPSFs.