Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Testing SRAM-Based Content Addressable Memories
IEEE Transactions on Computers
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
Automatic generation and compaction of March Tests for memory arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Design of Cache Test Hardware on the HP PA8500
IEEE Design & Test
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new framework for generating optimal March tests for memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Converting March Tests for Bit-Oriented Memories Into Tests for Word-Oriented Memories
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Disturb Neighborhood Pattern Sensitive Fault
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Highly-Efficient Transparent Online Memory Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Port Interference Faults in Two-Port Memories
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories
Journal of Electronic Testing: Theory and Applications
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
An Industrial Evaluation of DRAM Tests
IEEE Design & Test
Automatic march tests generations for static linked faults in SRAMs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
March test for static 3-coupling faults in random-access memories
DNCOCO'06 Proceedings of the 5th WSEAS international conference on Data networks, communications and computers
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Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration. This paper gives an overview of the most important and commonly used fault models, including the industry's popular disturb fault model. The fault coverage of march tests is analysed in a novel way, i.e., in terms of their detection capabilities for: simple faults, and linked faults; whereby the infinite class of linked faults has been reduced to a set of realistic linked faults. Thereafter the paper presents a methodology to design tests for realistic linked faults, resulting in the new tests March LR, March LRD and March LRDD. These new tests will be shown to be more efficient and to offer a higher fault coverage than comparable existing tests.