Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Address and Data Scrambling: Causes and Impact on Memory Tests
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Industrial Evaluation of DRAM SIMM Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tests for Resistive and Capacitive Defects in Address Decoders
ATS '01 Proceedings of the 10th Asian Test Symposium
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
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This application of 40 well-known memory tests to 1,896 1-Mbyte X 4 DRAM chips, used up to 48 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests' those covering more different functional faults' also have higher fault coverage.