Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
IEEE Transactions on Computers
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Industrial Evaluation of DRAM SIMM Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Industrial Evaluation of DRAM Tests
IEEE Design & Test
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents the results of ten well-known memorytest algorithms and four memory test primitives applied to3876 256Kbit SRAM chips, using 128 different stresscombinations with each test algorithm. The results showthat stress combinations influence the coverage of the testalgorithms for these SRAMs, and that the influence is lessfor these SRAMs than for DRAMs. Selecting the rightstress combination allows for using a simpler algorithm.The simple memory test primitives can detect all faultsgiven the proper stresses. Power supply voltage turns outto be a very important non-algorithmic stress.