Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Authors:
Ananta K. Majhi;Mohamed Azimane;Guido Gronthoud;Maurice Lousberg;Stefan Eichenberger;Fred Bowen
Affiliations:
Philips Research Laboratory, The Netherlands;Philips Research Laboratory, The Netherlands;Philips Research Laboratory, The Netherlands;Philips Research Laboratory, The Netherlands;Philips Semiconductors, The Netherlands;Philips Semiconductor, San Jose, CA
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

Citing 11
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Abstract

This paper presents the effectiveness of various stress conditions (mainly voltage and frequency) on detecting the resistive shorts and open defects in deep sub-micron embedded memories in an industrial environment. Simulation studies on very-low voltage, high voltage and at-speed testing show the need of the stress conditions for high quality products; i.e., low defect-per-million (DPM) level, which is driving the semiconductor market today.The above test conditions have been validated to screen out bad devices on real silicon (a test-chip) built on CMOS 0.18 um technology.IFA (inductive fault analysis) based simulation technique leads to an efficient fault coverage and DPM estimator, which helps the customers upfront to make decisions on test algorithm implementations under different stress conditions in order to reduce the number of test escapes.