Communications of the ACM
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Bridging Defects Resistance Measurements in a CMOS Process
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A New Algorithm for Dynamic Faults Detection in RAMs
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
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Embedded First-In First-Out (FIFO) memories are increasingly used in many IC designs. We have created a new full-custom embedded FIFO module with asynchronous read and write clocks, which is at least a factor two smaller and also faster than SRAM-based and standard-cell-based counterparts. The detection qualities of the FIFO test for both hard and weak resistive shorts and opens have been analyzed by an IFA-like method based on analog simulation. The defect coverage of the initial FIFO test for shorts in the bit-cell matrix has been improved by inclusion of an additional data background and low-voltage testing; for low-resistant shorts, 100% defect coverage is obtained. The defect coverage for opens has been improved by a new test procedure which includes waiting periods.