Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
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Resistive bridges not only cause a static faulty behavior in CMOS memories, but also lead to several dynamic faulty behaviors which are timing related failures. This paper introduces a new realistic dynamic fault model for random access-memories: the delay coupling fault, which models resistive bridges in the memory array.We show that well-known march tests do not ocver delay coupling faults at the memory array.To cover the delay coupling faults, a new and efficient test algorithm (DITEC+) is presented.We have performed inductive-fault analysis to validate this novel algorithm and shown a significant improvement on fault coverage.Also, experiment on silicon is carried out to show the existence of such dynamic faults and their detection by implementing DITEC+.